Semiconductor memories are a vital component of most digital logic systems. As such, advances in the fabrication of semiconductor memories that provide for higher integration densities and faster operating speeds may enhance the performance standards of many digital logic families. Semiconductor memory devices include volatile random access memories (RAMs) and non-volatile memory devices. In RAMs, data may be stored using a bistable flip-flop such as in a static random access memory (SRAM) or by charging a capacitor as in a dynamic random access memory (DRAM). IN either case, the stored data can be read out as long as power is applied to the memory device, but the data is lost when the power is turned off.
Non-volatile memories, such as, for example, MROM, PROM, EPROM and EEPROM memory devices are capable of storing data even when the power to the device is turned off. The non-volatile memory data storage mode may be permanenet or reprogrammable, depending upon the fabrication technology used. Non-volatile memories are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications and consumer electronics industries. A combination of single-chip volatile and non-volatile memory storage modes are also available in devices such as non-volatile SWAM (nvRAM) for use in systems that require fast, programmable non-volatile memory. In addition, dozens of special memory architectures have evolved which contain some additional logic circuitry to optimize their performance for application-specific tasks.
It typically is difficult or even impossible for general users of systems with Mesh ROM (“MROM”), Programmable ROM (“PROM”) or Erasable Programmable ROM (“EPROM”) memories to erase and write over information stored in the memory devices. On the other hand, Electrically Erasable Programmable ROM (“EEPROM”) memory devices can be erased and new data can be stored therein. As such, EEPROM memory devices are now widely used as auxiliary memories and/or to store system programming that requires periodic updates. Flash EEPROM devices generally have a higher degree of integration than do conventional EEPROM devices, and thus flash EEPROM memory devices are often used in applications that require a large auxiliary memory. NAND-type flash EEPROM memory devices (hereinafter, referred to as “NAND-type flash memory”) generally have a higher degree of integration than do NOR-type flash EEPROM memory devices.
FIG. 1 is a block diagram of the array structure of a conventional non-volatile memory device. As illustrated in FIG. 1, the memory cell array of the flash memory device includes a storage area for storing information, which may be divided into a main field 10 and a spare field 20. While the memory cell array depicted in FIG. 1 corresponds to a single memory block (or portion thereof), those of skill in the art will appreciate that typically the memory cell array will include many memory blocks. The spare field 20 may be used to store information related to the main field 10 as well as information such as error correction codes, device codes, other codes, page information and the like. Each of the main and spare fields 10 and 20 in the memory cell array includes a plurality of cell strings 1 (which are sometimes referred to as NAND strings) as illustrated in FIG. 1. A page buffer circuit (not illustrated in FIG. 1) is provided in the flash memory device to store data in and read data out of the memory cell array. As is well known in the art, memory cells of a NAND-type flash memory device may be programmed and erased using Fowler-Nordheim (“F-N”) tunneling current as disclosed, for example, in U.S. Pat. No. 5,473,563 entitled “NONVOLATILE SEMICONDUCTOR MEMORY” and U.S. Pat. No. 5,696,717 entitled “NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITY”, the disclosures of which are incorporated herein by reference as if set forth in their entirety.
In order to store data in the main field 10, a data loading command is applied to the flash memory device, and addresses and data are successively provided to the flash memory device. In general, data that is to be stored in the device is sequentially transferred to the page buffer circuit in a byte or word unit. Once a page of data is loaded into the page buffer circuit, the data is programmed into the memory cell array (that is, memory cells of the selected page) in response to a program command.
After the memory cells of a selected page are programmed, information indicating whether the memory cells of the selected page were programmed normally may be stored in a specific region (e.g., a spare field) of the memory cell array. Such information is often referred to as “page information” or as a “confirm mark.” The page information corresponding to pages WL0-WLm may, for example, be stored in a specific string of the spare field 20. For example, the page information corresponding to a first page WL0 may be stored in a memory cell M0′ of a string that is connected to spare bit line SBL0, the page information corresponding to a second page WL1 may be stored in a memory cell M1′ of the string that is connected to spare bit line SBL0, and the page information corresponding to the last page WLm may be stored in a memory cell Mm′ of the string that is connected to the spare bit line SBL0.
As should be clear from the above description, two program operations are required to store a pace data. Thus, if a memory cell array has 32 pages (or word lines), 64 program operations are required to store all 32 pages of data.